Abstract: This paper introduce a practical elimination of PLI (power line interference) with the frequency of 50 Hz and its 2nd, 3rd and 4th harmonics using digital FIR notch filter designed by FPGA chips Which is situated on development and education board DE2-70. To realize the filtering operation a digital multiband stop filter has been designed for frequencies 50Hz, 100Hz, 150Hz,and 200Hz with high order 1500 and processing word of 10bits and frequency 1000Hz to gain attenuation of 60dB for PLI signal components. Using FPGA to design digital FIR notch filter enable as of realization parallel processing to achieve digital convolution algorithm in the real time, where 1500 operation of adding, shifting, multiplying and dividing can be done in 0.5 ms (sampling period) for digital samples of 10 bits length, this equivalent 3 million operation per second where the general processor cannot do that.

Keywords: FPGA, DDFS, ECG, notch filer.